Many types of integrated circuits are fabricated using layers of conductive, semiconductive, and/or insulating materials. For example, an integrated circuit may include a substrate in which a number of active devices (such as transistors) are formed. Such active devices are then connected to one another by one or more conductive or semiconductive layers (referred to herein as "conducting layers"). The interconnecting conducting layers are separated from one another by insulating layers. Insulating and conducting layers are typically deposited according to a predetermined deposition "recipe" which may define the various materials, conditions and environment used to deposit a layer. Recipes may also be used to etch or pattern an insulating or conducting layer. For example, an etch recipe may be used to form contact holes in an insulating layer, while another set of recipes may be used to pattern a conducting layer.
Conducting layers may be composites of one or more conductive (or semiconductive) materials. As just a few examples, a conducting layer can include a first layer of conventionally doped polycrystalline silicon (polysilicon) and a second layer of "silicide" (silicon-metal alloy). Alternatively, a conducting layer can include a titanium(Ti)-tungsten(W) alloy layered onto bulk aluminum, with an underlying barrier layer comprising Ti, Ti-nitride (TiN), or a Ti alloy, to name just a few. Similarly, insulating layers can also be composites. As just one example, an insulating layer may include a "doped" silicon dioxide ("oxide") and an "undoped" silicon oxide. The doped silicon oxide can include dopant elements, such as boron and phosphorous, while the undoped silicon oxide will be essentially free of dopant elements.
Composite insulating layers and/or conducting layers can be undesirable as an increase in the number of layers used to form an integrated circuit generally results in a corresponding increase in the complexity and cost of the fabrication process. For example, a larger number of layers may result in a larger number of layer formation steps, and an increase in the "cycle time" (the time required to process a batch of wafers on which the integrated circuits are formed).
An insulating layer may perform a variety of functions in an integrated circuit. For example, an insulating layer may serve to electrically isolate one conducting layer or structure from another. Further, an insulating layer may serve as the surface on which subsequent layers are formed and patterned. Therefore, in many cases it is desirable for an insulating layer to provide a relatively planar surface. Planar surfaces are more desirable than non-planar surfaces, as typical, conventional lithographic patterning processes provide better results the more planar the surface. As just one example, certain photolithographic techniques using photoresist for producing relatively small structures can have more restricted fields of focus. If a layer on which photoresist is deposited is not planar, the photoresist may not adequately transfer the desired etch pattern. It is thus desirable to provide insulating layers with planar surfaces.
Connections between conducting layers may be made by structures referred to as contacts and "vias." A typical contact and/or via is formed by etching a hole through one or more insulating layers, and then filling the hole with a conductive or semiconductive material. One concern with certain contact structures is the alignment of the contact with a lower conducting layer. Because a contact is usually formed by etching a hole through an insulating layer to an underlying conducting layer, it is desirable for the etched hole to be situated directly over the desired contact location in the lower conducting layer.
Another concern regarding the formation of contacts is the etch process that is used to form a contact hole. In the event a contact hole is etched through a composite insulating layer, the etch process may include a different recipe for each of the different insulating materials in the composite layer. This can also increase cycle time and/or add to the complexity of the fabrication process.
Yet another concern regarding contacts and/or vias is the area of the contact. The area of a contact to a substrate can be of particular concern, as the substrate surface area also forms other important features, such as transistor channels, transistor isolation structures, transistor diffusion regions, and/or wells.
To better understand the formation of certain integrated circuit structures, including contacts, a conventional self-aligned contact (SAC) approach is set forth in FIGS. 7 and 8A-8I. FIG. 7 is a flowchart illustrating the general steps involved in forming a self-aligned contact for an integrated circuit that includes metal-oxide-semiconductor (MOS) transistors. FIGS. 8A-8I set forth a number of side cross-sectional views of a portion of an integrated circuit following the various steps described in FIG. 7.
The process set forth in FIG. 7 is designated by the general reference character 700, and begins by forming MOS field effect transistor (FET) gate structures (step 702). A portion of an integrated circuit following step 702 is set forth in FIG. 8A. MOSFET gate structures 800 are formed on a gate oxide layer 802. The gate oxide layer 802 is formed on a substrate 804. The MOSFET gate structures 800 include conductive portions 806 and insulating portions 808. In order to form as small a transistor as possible, the MOSFET gate structures 800 are patterned to have a desired minimum length (shown in the horizontal direction in FIG. 8A). Similarly, the distance between adjacent conductive portions 806 is likewise made as small as possible. Consequently, gate length and minimum spacing between adjacent conductive portions 806 may represent the patterning limits of an etch process. Minimum structure widths and structure separations, which may affect the overall operation of an integrated circuit, are often considered "critical dimensions" (CDs) that should be monitored during and/or after the fabrication of an integrated circuit to ensure proper performance. A substrate 804 may have wells formed therein by a previous substrate doping step. A substrate 804 may also include isolation structures formed therein by a previous substrate isolation structure forming step.
As set forth in FIG. 8B, following the formation of gate structures 800, diffusion regions 812 may be formed by doping the substrate 804 with predetermined dopants, usually to form p-n junctions. Such a doping step may include a source and/or drain doping step (which can include ion implantation and subsequent annealing steps) that can be used to form lightly doped diffusion structures, such as lightly doped drains (LDDs).
The process 700 continues by forming sidewalls on the gate structures (step 704). A portion of an integrated circuit following step 704 is set forth in FIG. 8B. Sidewalls 810 include insulating structures, and are shown to be formed on the sides of the gate structures 800. A conventional approach to forming sidewalls 810 includes forming an insulating layer over the gate structures 800, and subsequently anisotropically etching the insulating layer
Additional doping of diffusion regions 812 may occur following the formation of sidewalls 812. As just one example, a subsequent diffusion step (which can also include ion implantation and subsequent annealing steps) may be used to form diffusion structures, such as transistor sources and/or drains.
An important aspect of forming diffusion regions 812 is controlling their depth and/or lateral extent. Subjecting a diffusion region to temperature cycles following their initial formation can result in the dopants of the diffusion region diffusing deeper and/or further than desired, increasing the extents of the junction, and/or lowering the "abruptness" of a dopant concentration at the edge of a p-n junction. Too many temperature cycles may thus result in adverse transistor operation due to junction breakdown or "punch-through" current, to name just two examples. Consequently, the fabrication process of an integrated circuit may emphasize minimizing a device's exposure to temperature cycles (keeping as small a "thermal budget" as possible).
Following the formation of sidewalls 810, the conventional process 700 continues with the deposition of an insulating layer of boron and phosphorous doped silicon dioxide (borophosphosilicate glass, or "BPSG") (step 706). A portion of an integrated circuit following step 706 is set forth in FIG. 8C. Referring now to FIG. 8C, the BPSG layer 814 is shown to be deposited over the gate structures 800. In order to fill in, as much as possible, the space between adjacent gate structures 800, the BPSG may be deposited using chemical vapor deposition (CVD).
BPSG is a typical conventional choice for an insulating material due to its low "reflow" temperature. Reflow involves heating a layer so that the layer becomes more malleable, and thus flows to fill in the lowest lying space. The reflowed layer may thus become more planar than the originally deposited layer. Generally, the higher the concentration of boron and phosphorous, the lower the reflow temperature of the BPSG. BPSG is also desirable in that it can be a getterer for undesirable mobile ions, such as sodium, that can result in reliability failures in integrated circuits. Unfortunately, BPSG can have undesirable properties as well. The boron ions within BPSG can out-diffuse from the BPSG into the substrate, unintentionally doping the substrate. In addition, boron dopants can out-diffuse into polysilicon lines, unintentionally lowering or raising the conductivity of such lines.
While BPSG provides a relatively low reflow temperature, there are limits to BPSG reflow temperatures. Such limits arise out of the adverse effects presented by highly doped BPSG. Relatively high concentrations of boron (e.g., over 5% by weight) may make the resulting BPSG film unstable and hygroscopic (attract moisture). Unstable BPSG can crack and/or form boron rich crystals. BPSG cracks can ruin the insulating properties of the BPSG, while boron rich crystals may result in non-planar surfaces and/or micro-masking etch defects. The hygroscopic nature of conventional high-concentration BPSG can create bubbles, or result in forming one or more phosphorous-based acids, which may corrode conductive lines, such as those containing aluminum.
Another insulating material is phosphorous doped glass (phosphosilicate glass, or "PSG"). PSG is generally not used in conventional approaches due to its higher flow temperature. The flow temperature can be lowered by increasing the concentration of phosphorous, but higher concentrations of conventional PSG may have the drawbacks discussed above, including the formation of bubbles and/or acids.
Referring once again to FIG. 8C, the side cross-sectional view illustrates a drawback to using conventional BPSG to cover CD spacings. Conventional BPSG often contains voids 816 between minimum spaced structures (such as MOSFET gate structures 800). Voids 816 are undesirable as they can trap moisture and/or particles that can adversely affect the reliability of an integrated circuit. Further, if a void is exposed by a subsequent etch step, a conductive layer may unintentionally be deposited in a void 816, and not be removed by a patterning step. Such conductive layer residues may form "stringers" that can cause unwanted short circuits between conductive lines. Voids may also result in unpredictable etch results.
One way of describing a spacing between structures is with an "aspect ratio." An aspect ratio sets forth the ratio between a structure's height and its width. Constrained spaces having high aspect ratios (for example, aspect ratios greater than or equal to 7:1) may be difficult to fill without a reflow step.
Referring back to FIG. 7, the process 700 continues by reflowing the BPSG (step 708). As noted above, a reflow step can improve planarity of the deposited layer and improve the conformal nature of the BPSG. Reflow can also "density" the BPSG layer, decreasing the reactivity of the dopants to moisture and the like. Referring now to FIG. 8D, a side cross-sectional view of an integrated circuit following reflow is set forth. As shown by the figure, the reflow step has also served to eliminate the voids.
Following reflow (step 708), the BPSG layer is further planarized by chemical-mechanical polishing (CMP) (step 710). A side cross-sectional view of a portion of an integrated circuit following planarization is set forth in FIG. 8E. The upper surface of the BPSG layer 814 is planar, which may make the formation of subsequent structures easier.
Following planarization, a "cap" silicon oxide may be formed over the planarized BPSG layer (step 712). A portion of an integrated circuit following the deposition of a cap silicon oxide layer is set forth in FIG. 8F. The cap silicon oxide 818 may include undoped silicon dioxide and may serve to prevent the migration of the dopants from the BPSG or prevent moisture from migrating into the BPSG. Such a cap silicon oxide 818 may also provide a more stable surface for subsequent layers. Accordingly, the use of BPSG may result in a composite BPSG-cap silicon oxide layer. This may contribute to increases in cycle time and/or fabrication process complexity.
Once a BPSG is layer is capped, a contact etch mask may be formed (step 714). A portion of an integrated circuit following step 714 is set forth in FIG. 8G. The contact etch mask 820 is disposed over the cap silicon oxide 818, and includes openings where contact holes are to be formed.
Due to the composite nature of the deposited insulating layers (cap silicon oxide-BPSG), optimal formation of contact holes may be accomplished with a two step etch process. A first etch (step 716) is applied that may be optimized for the undoped cap silicon oxide 818. A second etch (step 718) may then be applied that is optimized for the BPSG 814. A side cross-sectional view of a portion of an integrated circuit following the first etch is set forth in FIG. 8H, while a side cross-sectional view of a portion of an integrated circuit following the second etch is set forth in FIG. 8I.
As shown in FIG. 8I, the resulting contact hole 822 is "self-aligned" with the MOSFET gate structures 800. The self-alignment occurs by the insulating portions 808 and sidewall portions 810 insulating the conductive portions 806 from the contact hole 822. As a result, there is no minimum spacing requirement between the edges of the contact hole 822 and the gate structures 800. The resulting structure may include conductive portions 806 separated from the contact hole 822 by an insulating structure (a sidewall 810 in the example of FIG. 8I) having a lateral width that is less than a critical dimension.
In light of the conventional approach set forth above, it would be desirable to provide an insulating material that allows for a smaller thermal budget than conventional approaches. It would also be desirable to provide an insulating material that reduces the cycle time and/or the complexity involved in fabricating an integrated circuit.